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19-3322; Rev 0; 8/04
I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller
General Description
The MAX6909/MAX6910 are real-time clocks (RTCs) with a microprocessor supervisor, optional trickle charger (MAX6910 only), backup power source, and NV RAM controller. The MAX6909/ MAX6910 provide alarm outputs to indicate a crystal failure, a switchover to battery power, and time and date indication. The NV RAM is 31 bytes of static RAM that are available for scratchpad storage. The MAX6909/ MAX6910 are controlled through a 2-wire serial bus. The real-time clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The date is automatically adjusted for months with fewer than 31 days, including corrections for leap year up to the year 2100. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. A time/date-programmable ALARM output completes the features list for the real-time clock section of the MAX6909/MAX6910. The alarm function can also be used in a polled mode by periodically reading the alarm out status bit in the minutes register. A crystal fail output, CX FAIL, indicates loss of accurate timekeeping due to crystal problems. A built-in P supervisor with an open-drain reset ensures the P powers up in a known state. A reset threshold is available for 3V or 3.3V supplies. The piezo transducer output, PZT, is register selectable for one of four frequencies, can be turned on and off through a register bit, or selected to go on when the ALM, alarm output, goes active. The MAX6909/MAX6910 are available in a 20-pin QSOP package and operate over the -40C to +85C temperature range. I2C-compatible
Features
RTC Counts Seconds, Minutes, Hours, Date of the Month, Month, Day of the Week, and Year, with Leap Year Compensation Valid Up to 2100 31 Bytes of RAM for Scratchpad Data Storage Uses Standard 32.768kHz, 6pF Load, Watch Crystal Programmable Time/Date, Open-Drain ALARM Output (Status Can also Be Polled) Chip Enable Gating (Control of CE with Reset and Power Valid) OUT Pin for SRAM Power P Reset Output Watchdog Input Manual Reset Input with Push-Button Switch Debounce Independent Power-Fail and Reset Comparators 400kHz 2-Wire Interface Single-Byte or Multiple-Byte (Burst Mode) Data Transfer for Read or Write of Clock Registers or RAM Bus Timeout to Prevent Lockup of Malfunctioning Bus Interface Dual Power-Supply Pins for Primary and Backup Power Programmable Trickle Charger (MAX6910) Uses Less than 1A Timekeeping Current at 3.0V Operating Voltages of 3V and 3.3V
MAX6909/MAX6910
Applications
Point-of-Sale Equipment Programmable Logic Controller Handheld Instruments Medical Instrumentation
PART MAX6909EO30 MAX6909EO33 MAX6910EO30 MAX6910EO33
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 20 QSOP 20 QSOP 20 QSOP 20 QSOP
Pin Configuration/Selector Guide/Typical Operating Circuit appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
ABSOLUTE MAXIMUM RATINGS
All Voltages (with respect to GND) BATT or VCC ..........................................................-0.3V to +6.0V OUT, ALM, SCL, SDA, CX FAIL, PFO, RESET.......................................................-0.3V to +6.0V All Other Pins ............................................-0.3V to (VSUP + 0.3V) (where VSUP is greater of VBATT or VCC) Input Current VCC ..............................................................................500mA BATT .............................................................................100mA GND ................................................................................20mA Output Current OUT Continuous............................................................450mA All Other Outputs ............................................................20mA Continuous Power Dissipation (TA = +70C) 20-Pin QSOP (derate 9.1mW/C above +70C)...........727mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range ............................ -65C to +150C Lead Temperature (soldering, 10s) ................................ +300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2)
PARAMETER Operating Voltage Range Operating Voltage Range BATT SYMBOL VCC VBATT CONDITIONS MAX69__EO30 (Note 3) MAX69__EO33 (Note 3) MAX69__EO30 (Note 4) MAX69__EO33 (Note 4) Crystal failcircuit disabled VBATT = 2V, VCC = 0V VBATT = 3V, VCC = 0V VBATT = 3.6V, VCC = 0V Timekeeping Current (Note 5) IBATT Crystal failcircuit enabled PZT disabled, crystal-disabled PZT disabled, crystal-disabled Crystal failcircuit enabled VBATT = 2V, VCC = 0V VBATT = 3V, VCC = 0V VBATT = 3.6V, VCC = 0V Active Supply Current (Note 6) Standby Current (Note 5) Standby Current (Note 5) Trickle-Charge Diode Voltage Drop (Two Diodes) R1 Trickle Charge Resistors OUT OUT in Battery-Backup Mode (Note 4) VBATT = 3.0V, VCC = 0V, IOUT = 20mA VOUT VBATT = 2.0V, VCC = 0V, IOUT 10mA VBATT 0.15 VBATT 0.1 VBATT - 0.1 V VBATT - 0.05 R2 R3 ICCA ICCS ICCS VCC = 3.3V, VBATT = 0V VCC = 3.6V, VBATT = 0V VCC = 3.3V, VBATT = 0V VCC = 3.6V, VBATT = 0V VCC = 3.3V, VBATT = 0V VCC = 3.6V, VBATT = 0V 1.2 1.7 2.8 5.0 k MIN 2.7 3.0 2.0 2.0 TYP MAX 3.3 3.6 3.6 3.6 0.75 0.95 1.1 0.9 4 9 0.14 0.15 7 7 18 25 mA A A V A A UNITS V V
BATT Current (Note 5)
IBATT
2
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller
ELECTRICAL CHARACTERISTICS (continued)
(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS VCC = 3.0V, VBATT = 0V, IOUT = 100mA OUT in VCC Mode (Note 4) VOUT VCC = 2.7V, VBATT = 0V, IOUT = 50mA VBATT to VCC Switchover Threshold VCC to VBATT Switchover Threshold CE IN AND CE OUT CE IN Leakage Current CE IN to CE OUT Resistance Disabled, VCC < VRST, V C E IN = VCC or GND VCC = VCC(min), VIH = 0.9VCC, VIL = 0.1VCC 50 source impedance driver, CLOAD = 10pF, VCC = VCC(MIN), VIH = 0.9VCC, VIL = 0.1 VCC (Note 8), measured from 50% point on CE IN to the 50% point on CE OUT tRCE MR low to high, VCC(MIN) < VCC < VCC(MAX) 2 -1 70 +1 140 A VTRU VTRD Power-up (VCC < VRST) switch from VBATT to VCC (Note 7) Power-down (VCC < VRST) switch from VCC to VBATT (Note 7) MIN VCC 0.15 VCC - 0.1 TYP VCC 0.1 V VCC 0.05 VBATT + 0.05 VBATT - 0.05 V V MAX UNITS
MAX6909/MAX6910
CE IN to CE OUT Propagation Delay
5
15
ns
RESET (or RESET) Active to CE OUT disabled and pulled to VOUT Delay CE OUT Enabled and Connected to CE IN After VCC > VRST CE OUT High (RESET or RESET Active) MANUAL RESET INPUT
10
50
s
tRP VOH VCC = 0V, IOUT = -100A, VBATT = 2V
140 0.95 x VOUT
200
280
ms V
VIL MR Input Threshold VIH MR Internal Pullup Resistance MR Minimum Pulse Width MR Glitch Immunity MR to Reset Delay PFI Input Threshold VPFT (Note 8) (Note 8) VCC = VCC(MIN) 1.19 200 1.27 1 0.7 x VCC 50
0.3 x VCC
V
k s 50 350 1.31 ns ns V
POWER-FAIL INPUT AND POWER-FAIL OUTPUT
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
ELECTRICAL CHARACTERISTICS (continued)
(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2)
PARAMETER PFI Input Current PFI to PFO Delay PFI Hysteresis PFO Output Voltage High PFO Output Voltage Low WATCHDOG INPUT Watchdog Timeout Period Initial Watchdog Timeout Period Minimum WDI Input Pulse Width tWD tWD tWDS tWDI VIL WDI Input Threshold VIH WDI Input Current PZT OUTPUT PZT Output Short-Circuit Current (VCC Must Be > VRST for PZT to Be Active) PZT Frequency 1 PZT Frequency 2 PZT Frequency 3 PZT Frequency 4 PZT Off-Leakage Current CRYSTAL-FAIL OUTPUT CX FAIL Output Low Voltage CX FAIL Off-Leakage Current ALARM OUTPUT ALM Output Low Voltage ALM Off-Leakage Current VOL IOLKG IOL = 3mA, VBATT = 2.0V, VCC = 0V IOL = 5mA, VCC = 2.7V, VBATT = 0V -1 0.2 0.25 +1 V A VOL IOLKG VBATT = 2.0V, VCC = 0V, IOL = 3mA VCC = 2.7V, IOL = 5mA, VBATT = 0V -1 0.1 0.2 0.25 +1 V A MAX69_ _EO30 IPZT MAX69_ _EO33 PZTf1 PZTf2 PZTf3 PZTf4 IOLKG -1 Sink current Source current Sink current Source current 5 5 6 6.5 1024 2048 4096 8192 +1 18 20 20 25 Hz Hz Hz Hz A mA IIL VWDI = VCC or GND 0.7 x VCC -100 +100 nA Before first WDI edge, after reset timeout Register select--long Register select--short 1.00 1.00 140 100 0.3 x VCC 1.6 1.6 200 2.25 2.25 280 s s ms ns VPFH VOH VOL (Note 8) PFI rising ISOURCE = 200A, PFI = VCC = VCC(MIN) ISINK = 1.2mA, VBATT = 2V, PFI = VCC = 0V 0.9 x VCC 0.2 PFI rising PFI falling SYMBOL CONDITIONS MIN -100 0.06 2.4 TYP +2 0.2 5 30 MAX +100 2.2 12 UNITS nA s mV V V
V
4
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller
ELECTRICAL CHARACTERISTICS (continued)
(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2)
PARAMETER BATTERY ON OUTPUT BATT ON Output Low Voltage BATT ON Off-Leakage Current RESET FUNCTION Reset Threshold VRST Hysteresis VCC Falling Reset Delay Reset Active Timeout Period RESET Output Low Voltage RESET Off-Leakage Current tRP VOL ILKG IOH = 50A, VCC = 1.0V, VBATT = 0V IOH = 1mA, VCC = 2V, VBATT = 0V VCC = VCC(MIN), IOL = 1.6mA 0.7 x VCC 0.3 x VCC 0.05 x VCC VIN = GND or VCC (Note 8) VOL IOL = 4mA, VCC = VCC(MIN) -1 +1 10 0.4 Reset asserted IOL = 1.6mA, VBATT = 2.0V, VCC = 0V -1 0.8 x VCC 0.9 x VCC 0.032 0.1 V VRST VHYST VCC falling from VRST(MAX) to VRST(MIN) at 10V/ms, measured from the beginning of VCC falling to RESET asserting high 140 MAX69_ _EO33 MAX69_ _EO30 2.80 2.50 2.93 2.63 10 10 200 50 280 0.2 +1 3.00 2.70 V mV s ms V A VOL IOLKG VBATT = 2.0V, IOL = 3mA, VCC = 0V VBATT = 2.7V, IOL = 5mA, VCC = 0V -1 0.2 0.25 +1 V A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX6909/MAX6910
RESET Output High Voltage
VOH
Reset asserted
V
RESET Output Low Voltage
VOL
2-WIRE DIGITAL INPUTS (SCL, SDA) (VCC(MIN) < VCC < VCC(MAX)) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance Output Low Voltage VIH VIL VHYS V V V A pF V
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
AC ELECTRICAL CHARACTERISTICS
(VCC(MIN) < VCC < VCC(MAX), TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER 2-WIRE BUS TIMING SCL Clock Frequency Bus Timeout Bus Free Time Between STOP and START Condition Hold Time After (Repeated) START Condition; After This Period, the First Clock Is Generated Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Setup Time SCL Low to Data Out Valid SCL Low Period SCL High Period SCL/SDA Rise Time SCL/SDA Fall Time (Receiving) SCL/SDA Fall Time (Transmitting) Pulse Width of Spike Suppressed Capacitive Load of Each Bus Line fSCL tTIMEOUT tBUF (Note 9) 0.32 1 1.3 400.00 2 kHz s s SYMBOL CONDITIONS MIN TYP MAX UNITS
tHD:STA
0.6
s
tSU:STA tSU:STO tHD:DAT tSU:DAT tVD:DAT tLOW tHIGH tR tF tF tSP CB (Note 12) (Notes 12, 13) (Notes 12, 13) (Note 8) (Note 8) (Notes 10, 11)
0.6 0.6 0 100 50 1.3 0.6 20 + 0.1 x CB 20 + 0.1 x CB 20 + 0.1 x CB 300 300 250 50 400 0.9
s s s ns ns s s ns ns ns ns pF
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13:
VRST is the reset threshold for VCC. See the Ordering Information. All parameters are 100% tested at TA = +85C. Limits over temperature are guaranteed by design and not production tested. 2-wire serial interface is operational for VCC > VRST. See the Detailed Description section (BATT function). IBATT and ICCS are specified with SDA and SCLK pulled high, OUT floating, and CE OUT floating. 2-wire serial interface operating at 400kHz, SDA pulled high. For OUT switch over to BATT, VCC must fall below VRST and VBATT. For OUT switchover to VCC, VCC must be above VRST or above VBATT. Guaranteed by design. Not production tested. Due to the 2-wire bus timeout feature, there is a minimum specification on the SCL clock frequency based on a 31-byte burst-mode transaction to RAM. See the Timeout Feature section. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. CB = total capacitance of one bus line in pF. The maximum tF for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tF is specified at 250ns. This allows series protection resistors to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tF.
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
Typical Operating Characteristics
(VCC = 3.3V, VBATT = 3V, TA = +25C, unless otherwise noted.)
VCC TO OUT VOLTAGE vs. TEMPERATURE
MAX6909/10 toc01
BATT-TO-OUT VOLTAGE vs. TEMPERATURE
MAX6909/10 toc02
BATT TIMEKEEPING CURRENT vs. TEMPERATURE
VBATT = 3V VCC = 0V CRYSTAL FAIL-DETECTION DISABLED
MAX6909/10 toc03
100
350 VBATT = 2V VCC = 0V IOUT = 50mA
700 BATT TIMEKEEPING CURRENT (nA) 650 600 550 500 450 400
80
VCC = 3V VBATT = 0V IOUT = 100mA
BATT-TO-OUT VOLTAGE (mV)
VCC TO OUT VOLTAGE (mV)
90
300
250
70 VCC = 3.3V VBATT = 0V IOUT = 100mA
200 VBATT = 3.0V VCC = 0V IOUT = 50mA -40 -15 10 35 60 85
60
150
50 -40 -15 10 35 60 85 TEMPERATURE (C)
100 TEMPERATURE (C)
-40
-15
10
35
60
85
TEMPERATURE (C)
RESET TIMEOUT PERIOD vs. TEMPERATURE
MAX6909/10 toc04
RESET COMPARATOR DELAY vs. VCC FALLING
MAX6909/10 toc05
RESET COMPARATOR DELAY vs. TEMPERATURE
24 23 RESET DELAY (s) 22 21 20 19 18 17 VCC FALLING AT 10V/ms
MAX6909/10 toc06
220 215 TIMEOUT PERIOD (ms) 210 205 200 195 190 185 180 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C)
1000
25
100 RESET DELAY (s)
10
1
16 0.1 0.1 1 10 VCC FALLING (V/ms) 100 1000 15 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C)
RESET THRESHOLD vs. TEMPERATURE
MAX6909/10 toc07
PFI THRESHOLD vs. TEMPERATURE
1.243 1.242 PFI THRESHOLD (V) 1.241 1.240 1.239 1.238 1.237 1.236 1.235 1.234 0.1 -40 -25 -10 5 20 35 50 65 80 1
MAX6909/10 toc08
PFI-TO-PFO DELAY vs. PFI FALLING
MAX6909/10 toc09
3.100 3.095 3.090 RESET THRESHOLD (V) 3.085 3.080 3.075 3.070 3.065 3.060 3.055 3.050 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C)
1.244
100
PFO DELAY (s)
10
1
10
100
1000
TEMPERATURE (C)
PFI FALLING (V/ms)
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
Typical Operating Characteristics (continued)
(VCC = 3.3V, VBATT = 3V, TA = +25C, unless otherwise noted.)
WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE
MAX6909/10 toc10 MAX6909/10 toc11
PFI-TO-PFO DELAY vs. TEMPERATURE
13.0 12.5 PFO DELAY (s) 12.0 11.5 11.0 10.5 10.0 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C) 1.700 WATCHDOG TIMEOUT PERIOD (ms) 1.695 1.690 1.685 1.680 1.675 1.670 1.665 1.660 PFI FALLING AT 10V/ms
CE_IN TO CE_OUT ON-RESISTANCE vs. VCC
CE_IN TO CE_OUT ON-RESISTANCE () VCE_IN = 0.9 x VCC 110
MAX6909/10 toc12
120
100
90
80
-40 -25 -10
5
20
35
50
65
80
70 2.7 3.0 3.3 3.6 VCC VOLTAGE (V)
TEMPERATURE (C)
CE_IN TO CE_OUT ON-RESISTANCE vs. TEMPERATURE
MAX6909/10 toc13
PZT OUTPUT RESISTANCE vs. VCC
PZT OUTPUT RESISTANCE = (VBATT/ISINK + VCC/ISOURCE) / 2
MAX6909/10 toc14
120 CE_IN TO CE_OUT ON-RESISTANCE () VCE_IN = 0.9 x VCC 110 100 90 80 VCC = VRST + 0.1V = 3.03V 70 60 -40 -15 -10 35 60 VCC = VRST + 0.1V = 2.73V
70 65 60 55 50 45 40
PZT OUTPUT RESISTANCE ()
85
2.7
3.0
3.3
3.6
TEMPERATURE (C)
VCC VOLTAGE (V)
PZT OUTPUT RESISTANCE vs. TEMPERATURE
MAX6909/10 toc15
MAXIMUM TRANSIENT DURATION vs. RESET COMPARATOR OVERDRIVE
MAXIMUM TRANSIENT DURATION (s) 90 80 70 60 50 40 30 20 10 0 0 50 100 150 200 250 300 350 400 450 500 OVERDRIVE (mV) RESET ASSERTS ABOVE THIS LINE
MAX6909/10 toc16
80
100
PZT OUTPUT RESISTANCE ()
70
60
VCC = 3V
50 VCC = 3.3V 40
30 -40 -15 10 35 60 85 TEMPERATURE (C)
8
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME BATT OUT BATT ON CE IN PFI MR WDI GND X1 X2 CX FAIL SDA SCL ALM PZT PFO CE OUT RESET RESET VCC FUNCTION Backup Battery Input. When VCC falls below the reset threshold and VBATT, OUT connects to BATT. Connect BATT to GND if no backup battery supply is used. Supply Output for CMOS RAM or Other ICs Requiring Use of Backup Battery Power. Bypass to GND with at least a 0.1F capacitor. Logic Output Open Drain. BATT ON is low when the MAX6909/MAX6910 are powered from BATT. Chip-Enable Input. Input to the chip-enable switch used for external RAM. Connect to VCC if unused. Power-Fail Comparator Input. For monitoring external power supplies. Manual Reset Input. The active-low input has an internal pullup resistor. Internal debouncing circuitry ensures noise immunity. Leave open if unused. Watchdog Input Ground 32.768kHz Crystal Pin; Oscillator Input 32.768kHz Crystal Pin; Oscillator Output Crystal Fail Output. Open drain, active low. Serial Data Line. Data input/output connection for the 2-wire serial interface. Serial Clock Line. Clock input connection for the 2-wire serial interface. Alarm Output. Open drain, active low. Piezo Transducer Output. Push-pull Piezo transducer output. Power-Fail Comparator Output. Push-pull active low. Chip-Enable Output. For controlling external RAM. Open-Drain, Active-Low Reset Output Push-Pull, Active-High Reset Output. Complement of RESET. Main Supply Input. Bypass to GND with at least a 0.01F capacitor.
MAX6909/MAX6910
Detailed Description
The MAX6909/MAX6910 contain eight 8-bit timekeeping registers, two burst address registers, a trickle charge register, a control register, a configuration register, an alarm configuration register, and seven alarm threshold registers, all controlled through a 2-wire serial interface. Figure 1 is the MAX6909/MAX6910 block diagram. The OUT pin supplies voltage for CMOS RAM or other ICs requiring the use of backup battery power. When VCC rises above the reset threshold (VRST) or above VBATT, OUT is connected to VCC. When VCC falls below VRST and VBATT, BATT is connected to OUT. If enabled, an on-board trickle charger charges BATT from VCC. BATT can act as a backup supply from either a battery or SuperCapTM. When operating from BATT, the batteryon output (BATT ON) is pulled low and can be used as an indicator of operation in battery backup mode.
SuperCap is a trademark of Baknor Industries.
There are two reset outputs, RESET and RESET. They become active while VCC is below the reset threshold (VRST) or while manual reset (MR) is held low, and for t RP after MR goes high, V CC rises above the reset threshold, or a WDI pulse is not received when the watchdog function is enabled. Reset thresholds are available for 3V and 3.3V applications. See the Ordering Information for specifics. MR is internally pulled high and contains debounce circuitry to accommodate a manual pushbutton reset switch. The WDI, when enabled, keeps RESET and RESET from becoming active if it is strobed once every tWDS or tWD. The watchdog timeout is selectable in the configuration register. Other features include internal chip-enable gating logic, which accepts a valid CE IN from a microprocessor and only gates it through as valid to CE OUT when the MAX6909/MAX6910 are not in a reset state. This can be used for disabling CMOS RAM to limit current consumption when OUT is switched to BATT.
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
X1 X2 OSCILLATOR 32.768kHz DIVIDERS FREQUENCY SELECT PZT
CX_FAIL
CRYSTALFAIL DETECT WATCHDOG TIMER DEBOUNCE CIRCUIT
SOURCE SELECT
WDI
RESET RESET LOGIC RESET
MR
PFI 1.2V
PFO
CE_IN 1Hz
CE CONTROL
CE_OUT
SECONDS MINUTES HOURS DATE MONTH
BATT OUT VCC GND BATT_ON POWER CONTROL CONTROL LOGIC
DAY YEAR CONTROL TRICKLE CHARGER CENTURY
SCL SDA
INPUT SHIFT REGISTERS
ADDRESS REGISTER
ALARM CONFIG TEST CONFIG
31 x 8 RAM
CX STATUS CONFIG ALARM THRESHOLDS CLK BURST
ALM ALARM CONTROL LOGIC
RAM BURST
Figure 1. MAX6909/MAX6910 Block Diagram 10 ______________________________________________________________________________________
I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller
A power-fail comparator is available to monitor other system voltages through PFI and report the status through PFO. If the MAX6909/MAX6910 are in reset, PFO is low; otherwise, it is high as long as PFI is greater than 1.27V (typ). The piezo transducer drive output (PZT) has registerselectable frequencies of 1.024kHz, 2.048kHz, 4.096kHz, or 8.192kHz. This output can be selected to become active when the alarm is triggered or can be independently controlled through the configuration register. When activated, the PZT outputs a frequency with an attention-getting 1Hz duty cycle of 50% on and 50% off. An on-chip crystal oscillator maintaining circuit, for use with a 32.768kHz crystal, provides the clock for timekeeping functions. A crystal fail output (CX FAIL) alerts the user when the 32.768kHz crystal oscillator has failed for 30 cycles (typ), resulting in conditions that produce invalid timekeeping data. The crystal fail function can also be polled by reading the status bit in the CX status register. itance (CL) of 6pF where the capacitive load is included in the MAX6909/MAX6910. When designing the PC board, keep the crystal as close to the X1 and X2 pins as possible. Keep the trace lengths short and small and place a guard ring around the crystal and connect the ring to GND to reduce capacitive loading and prevent unwanted noise pickup. Keep all signals out from beneath the crystal and the X1 and X2 pins to prevent noise coupling. Finally, an additional local ground plane on an adjacent PC board layer can be added under the crystal to shield it from unwanted pickup from traces on other layers of the board. This plane should be isolated from the regular PC board ground plane, should be no larger than the perimeter of the guard ring, and connected to the GND pin of the MAX6909/MAX6910. Ensure that this ground plane does not contribute to significant capacitance between signal line and ground on the connections that run from X1 and X2 to the crystal. Figure 2 shows the recommended crystal layout. Some crystal manufacturers and part numbers for their SMT, 32.768kHz watch crystals that require 6pF loads are listed in Table 1. In addition, these manufacturers offer other package options depending upon the specific application considerations.
MAX6909/MAX6910
Crystal Selection
A 32.768kHz crystal is connected to the MAX6909/ MAX6910 through pins 9 and 10 (X1 and X2). The crystal selected for use should have a specified load capac-
GROUND PLANE VIA CONNECTION MAX6909/MAX6910 GUARD RING * * ** * * * *
* * *
10 11
SM WATCH CRYSTAL *
** * GROUND PLANE VIA CONNECTION *LAYER 1 TRACE **LAYER 2 LOCAL GROUND PLANE CONNECT ONLY TO PIN 8 GROUND PLANE VIA CONNECTION **
Figure 2. Recommended Crystal Layout ______________________________________________________________________________________ 11
I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
Table 1. Crystal Manufacturers and Part Numbers
MANUFACTURER Caliber Electronics ECS INC International Fox Electronics M-tron Raltron PART AWS2A-32.768KHz, AWS2B-32.768KHz ECS-.327-6.0-17 FSM327 SX2010/ SX2020 RSE-32.768-6-C-T TEMP RANGE (C) -20 to +70 -10 to +60 -40 to +85 -20 to +75 -10 to +60 CL (pF) 6 6 6 6 6 +25C FREQUENCY TOLERANCE (ppm) 20 20 20 20 20
Timekeeping accuracy of the MAX6909/MAX6910 is dependent on the frequency stability of the external crystal. To determine frequency stability, use the parabolic curve of Figure 3 and the following equations: f = f k (T0 - T)2 where: f = change in frequency from +25C (Hz) f = nominal crystal frequency (Hz) k = parabolic curvature constant (-0.035 0.005ppm/C2 for 32.768kHz watch crystals) T0 = turnover temperature (+25C 5C for 32.768kHz watch crystals) T = temperature of interest (C) For example: What is the worst-case change in oscillator frequency from +25C ambient to +45C ambient?
fdrift = 32,768Hz (-0.04ppm/C)2 (20C - 45C)2 = -0.8192Hz What is the worst-case timekeeping error per second? 1) Error due to temperature drift: tdrift {[1 / [(f + fdrift) / 32,768]] - 1s} / 1s tdrift {[1 / [(32,768Hz - 0.8192Hz) / 32,768]] - 1s} / 1s = 0.000025s / s 2) Error due to +25C initial crystal tolerance of 20ppm: finitial = 32,768Hz (-20ppm) = -0.65536Hz tinitial = {[1 / [(f + finitial) / 32,768]] - 1} / 1s tinitial = {[1 / [32,768 - 0.65536 / 32,768]] - 1} / 1s = 0.000020s / s 3) Total timekeeping error per second: ttotal = tdrift + tinitial
ttotal = 0.000025s / s + 0.000020s / s = 0.000045 s / s
TYPICAL TEMPERATURE CHARACTERISTICS (k = -0.035ppm/C2; TO = +25C)
0
Rf MAX6909
-50
f (ppm)
-100
Rd
-150
Cg 12pF
Cd 12pF
-200
-250 -50-40-30-20-10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C)
X1
X2 EXTERNAL CRYSTAL
Figure 3. Frequency Stability and Temperature 12
Figure 4. Oscillator Functional Schematic
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller
Table 2. Acceptable Quartz Crystal Parameters
PARAMETER Frequency Equivalent series resistance (ESR) Parallel load capacitance Q factor SYMBOL f RS CL Q 40,000 6 MIN TYP 32.768 60 MAX UNITS kHz k pF
MAX6909/MAX6910
After 1 month that translates to: hr min s t = (31day) x 24 x 60 x x 60 hr min day
RAM
The static RAM is 31 bytes addressed consecutively in the RAM address space. Even address/commands (C0h-FCh) are used for writes, and odd address/commands (C1h-FDh) are used for reads. The contents of the RAM are static and remain valid for VOUT down to 1.5V (typ).
(0.000045s / s) = 120.158s
Total worst-case timekeeping error at the end of 1 month at +45C is approximately 120s or 2min (assumes negligible parasitic layout capacitance). Figure 5 shows the register address definition. Table 3 is the hex register address/description.
RAM Burst
Addressing the RAM burst register specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively read or written starting with bit 7 of address FEh for a write and FFh for a read. When writing to RAM in burst mode, it is not necessary to write all 31 bytes for the data to transfer. Each byte that is written to is transferred to RAM regardless of whether all 31 bytes are written.
Control Register (Write Protect Bit)
Bit 7 of the control register is the write protect bit. The lower 7 bits (bits 0-6) are forced to zero and always read a zero when read. Before any write operation to the clock or RAM, bit 7 must be zero. When high, the write protect bit prevents a write operation to any other register.
Trickle Charge Register (MAX6910)
The trickle charge register controls the trickle charger characteristics of the MAX6910. The trickle charger functional schematic (Figure 6) shows the basic components of the trickle charger. Table 4 details the bit settings for trickle charger control. Trickle charge selection (TCS) bits D7-D4 control the selection of the trickle charger. In order to prevent accidental enabling, only a pattern of 1010 enables the trickle charger. All other patterns disable the trickle charger. The MAX6910 powers up with the trickle charger disabled. The diode select (DS) bits (D3-D2) select whether two diodes or no diodes are connected between VCC and BATT. If DS is 10, no diode is selected; if DS is 01, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled independent of the state of the TCS bits. The RS bits (D1-D0) select the resistor that is connected between VCC and BATT. If both RS bits are set to zero, the trickle charger is disabled, regardless of any other bit states in the trickle charger register. RS bits set to 10 select a 1.7K, 01 selects 2.9K, and 11 select 5K.
Hours Register (AM-PM/12-24 Mode)
Bit 7 of the hours register is defined as the 12-hour or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20h-23h).
Clock Burst
Addressing the clock burst register specifies burst mode operation. In this mode, the first seven clock/calendar registers and the control register can be consecutively read or written starting with bit 7 of address BEh for a write and BFh for a read. If the write protect bit is set high when a write clock/calendar burst mode is specified, no data transfer occurs to any of the seven clock/calendar registers or the control register. When writing to the clock registers in the burst mode, all eight registers must be written in order for the data to be transferred. In addition, the WP bit in the control register must be set to zero prior to a clock burst write.
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
REGISTER ADDRESS FUNCTION SEC A7 1 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 RD /W MIN 1 0 0 0 0 0 1 RD /W *POR STATE HR 1 0 0 0 0 1 0 RD /W 00-23 12/24 0 01-12 *POR STATE DATE 1 0 0 0 0 1 1 RD /W 01-28/29 01-30 01-31 *POR STATE MONTH 1 0 0 0 1 0 0 RD /W DAY 1 0 0 0 1 0 1 RD /W YEAR 1 0 0 0 1 1 0 RD /W CONTROL 1 0 0 0 1 1 1 RD /W TRICKLE CHARGER 1 0 0 1 0 0 0 RD /W 1 0 0 1 0 0 1 RD /W ALARM CONFIG 1 0 0 1 0 1 0 RD *POR STATE 00-99 *POR STATE 0 CX FAIL EN *POR STATE 01-12 *POR STATE 01-07 *POR STATE 00-99 *POR STATE 0 WP 0 TCS 0 1/0 0 0 10 HR A/P 0/1 0 10 HR 0 0 0 1 HR 0 0 VALUE 00-59 *POR STATE 00-59 REGISTER DEFINITION D7 0 0 ALM OUT 0 0 0 D6 D5 10 SEC 0 10 MIN 0 0 0 0 0 0 0 D4 D3 D2 D1 D0
1 SEC 0 1 MIN 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
10 DATE 0 0 0 0 0 0 10 M 0 0 0 0 0 0 0
1 DATE 0 0 1
1 MONTH 0 0 WEEKDAY 0 0 1 1
10 YEAR 1 0 0 TCS 0 1 0 0 TCS 0 1 0 0 TCS 0 0 0 0 DS 0
1 YEAR 0 0 0 DS 0 0 0 0 RS 0 0 0 0 RS 0
CENTURY
1000 YEAR 0 0 1 MONTH 1
100 YEAR 0 0 1
HOUR
YEAR
DATE
DAY
MIN 0 1 1
/W TEST CONFIG 1 0 0 1 0 1 1 RD
*POR STATE
0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 1 1
*POR STATE
0
NOTE: *POR STATE DEFINES POWER-ON RESET STATE OF REGISTER CONTENTS. THE TEST CONFIG REGISTER IS A READ-ONLY REGISTER.
Figure 5. Register Address Definition (Sheet 1 of 2)
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SEC 0 1 1
I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
REGISTER ADDRESS FUNCTION CX STATUS A7 1 A6 0 A5 0 A4 1 A3 1 A2 0 A1 0 A0 RD /W *POR STATE CONFIG 1 0 0 1 1 0 1 RD /W *POR STATE ALARM THRESHOLDS: SEC VALUE REGISTER DEFINITION D7 CX FAIL 0 WD EN 0 D6 0 0 0 0 D5 0 0 0 0 D4 0 0 WD TIME 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0
PZT PZT PZT PZT SEL CNTL REFQ FREQ 0 0 0 0
1
0
0
1
1
1
0
RD /W
00-59 *POR STATE 00-59 *POR STATE
0 0 0 0 1 1
10 SEC 1 10 MIN 1 10 HR A/P 0/1 1 1 1 1 1 1 1
1 SEC 1 1 MIN 1 1 1
MIN
1
0
0
1
1
1
1
RD /W
HR
1
0
1
0
0
0
0
RD /W
00-23 12/24 0 01-12 *POR STATE 1/0 1 0
10 HR 1 1 1
1 HR 1 1
DATE
1
0
1
0
0
0
1
RD /W
01-28/29 01-30 01-31 *POR STATE
0 0 0 0 0 0
0 0 0 0 0 0
10 DATE 1 0 0 0 0 1 10 M 1 0 0 1 0 0 1
1 DATE 1 1 1
MONTH
1
0
1
0
0
1
0
RD /W
01-12 *POR STATE 01-07 *POR STATE 00-99 *POR STATE
1 MONTH 1 1 WEEKDAY 0 0 0 1
DAY
1
0
1
0
0
1
1
RD /W
YEAR
1
0
1
0
1
0
0
RD /W
10 YEAR 1 1 1 1 1
1 YEAR 1 1 1
CLOCK BURST RAM RAM 0
1
0
1
1
1
1
1
RD /W
1
1
0
0
0
0
0
RD /W
RAM DATA 0
X
X
X
X
X
X
X
X
RAM 30
1
1
1
1
1
1
1
RD /W
RAM DATA 30
X
X
X
X
X
X
X
X
RAM BURST
1
1
1
1
1
1
1
RD /W
NOTE: *POR STATE DEFINES POWER-ON RESET STATE OF REGISTER CONTENTS.
Figure 5. Register Address Definition (Sheet 2 of 2) ______________________________________________________________________________________ 15
I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
Table 3. Hex Register Address/Description
WRITE (HEX) 80 82 84 86 88 8A 8C 8E 90 92 94 -- 98 9A 9C 9E A0 A2 A4 A6 A8 BE C0 C2 C4 C6 C8 CA CC CE D0 D2 D4 D6 D8 DA DC DE E0 E2 READ (HEX) 81 83 85 87 89 8B 8D 8F 91 93 95 97 99 9B 9D 9F A1 A3 A5 A7 A9 BF C1 C3 C5 C7 C9 CB CD CF D1 D3 D5 D7 D9 DB DD DF E1 E3 Seconds Minutes Hours Date Month Day Year Control Trickle charger Century Alarm configuration Test configuration* CX status Configuration Seconds alarm threshold Minutes alarm threshold Hours alarm threshold Date alarm threshold Month alarm threshold Day alarm threshold Year alarm threshold Clock burst RAM 0 RAM 1 RAM 2 RAM 3 RAM 4 RAM 5 RAM 6 RAM 7 RAM 8 RAM 9 RAM 10 RAM 11 RAM 12 RAM 13 RAM 14 RAM 15 RAM 16 RAM 17 DESCRIPTION POR CONTENTS (HEX) 00 00 00 01 01 01 70 00 00 19 00 07 00 00 7F 7F BF 3F 1F 00 FF N/A Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate POR CONTENTS (BCD) 00 00 00 01 01 01 70 00 00 19 00 07 00 00 7F 7F BF 3F 1F 00 FF N/A Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller
Table 3. Hex Register Address/Description (continued)
WRITE (HEX) E4 E6 E8 EA EC EE F0 F2 F4 F6 F8 FA FC FE READ (HEX) E5 E7 E9 EB ED EF F1 F3 F5 F7 F9 FB FD FF RAM 18 RAM 19 RAM 20 RAM 21 RAM 22 RAM 23 RAM 24 RAM 25 RAM 26 RAM 27 RAM 28 RAM 29 RAM 30 RAM Burst DESCRIPTION POR CONTENTS (HEX) Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate N/A POR CONTENTS (BCD) Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate N/A
MAX6909/MAX6910
Diode and resistor selection is determined by the user, according to the maximum current desired for the battery or SuperCap charging. The maximum charging current can be calculated as shown in the following example. Assume that a system power supply of 3V is applied to VCC and a SuperCap is connected to BATT. Also assume that the trickle charger has been enabled with no diode and resistor R1 between VCC and BATT. The maximum current IMAX would therefore be calculated as follows: IMAX = 3.0V 3.0V 1.76mA R1 1.7k
As the SuperCap charges, the voltage difference between VCC and VBATT decreases, and therefore the charge current decreases. The MAX6909 does not feature a trickle charger.
Power Control, Trickle Charger, and Battery Switchover
BATT provides power as a battery backup. VCC provides the primary power in dual-supply systems where BATT is connected as a backup source to maintain the timekeeping function and RAM + register contents. When VCC rises above the reset threshold, VRST, VCC powers the MAX6909/MAX6910. When VCC falls below the reset
threshold, VRST, and is less than VTPD, BATT powers the MAX6909/MAX6910. If VCC falls below the reset threshold, V RST , and is more than V TPD , V CC powers the MAX6909/MAX6910. When RESET and RESET are active, all inputs (MR, WDI, CE IN, and the 2-wire interface) are disabled. In addition, when operating from BATT, the outputs RESET, RESET, and PFO remain in the active state, PZT is high impedance and CE OUT is pulled to OUT. The timekeeping function remains active, together with the alarm function and crystal fail function if enabled. To minimize power consumption when operating from BATT, some functions are disabled; see Table 5. MAX6909/ MAX6910 functional blocks remain active when powered from VCC or BATT. A battery can be connected prior to application of VCC with no current being drawn from the battery and the MAX6909/MAX6910 remaining inactive. This is the freshness seal mode of operation. On the very first application of V CC to the MAX6909/MAX6910, V CC must rise above the reset threshold. The battery should only be changed with VCC applied in order to maintain timekeeping functions. The trickle charger can be enabled and disabled through software control but is automatically disabled whenever VCC falls below VBATT.
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
Table 4. Trickle-Charger Register Control
D7 TCS X X X 1 1 1 1 1 1 D6 TCS X X X 0 0 0 0 0 0 D5 TCS X X X 1 1 1 1 1 1 D4 TCS X X X 0 0 0 0 0 0 D3 DS 0 1 X 1 1 1 0 0 0 D2 DS 0 1 X 0 0 0 1 1 1 D1 RS X X 0 1 0 1 1 0 1 D0 RS X X 0 0 1 1 0 1 1 Trickle charger disabled Trickle charger disabled Trickle charger disabled No diode selected; 1.7K selected No diode selected; 2.9K selected No diode selected; 5K selected Two diodes selected; 1.7K selected Two diodes selected; 2.9K selected Two diodes selected; 5K selected ACTION
R1 1.7k R2 2.9k R3 5k PIN 20 BATT
VCC
PIN 1
1 OF 16 SELECT (NOTE: ONLY 1010 CODE ENABLES CHARGER)
1 OF 2 SELECT
1 OF 3 SELECT TCS = TRICKLE CHARGER SELECT DS = DIODE SELECT RS = RESISTOR SELECT
TRICKLE CHARGE
TCS
TCS BIT 6
TCS BIT 6
TCS BIT 4
DS BIT 3
DS BIT 2
RS BIT 1
RS BIT 0
REGISTER BIT 7
Figure 6. Trickle-Charger Functional Schematic
OUT Function
OUT is an output supply voltage for external devices. When VCC rises above the reset threshold or is greater than VBATT, OUT connects to VCC. When VCC falls below VRST and VBATT, OUT connects to BATT. There is a typical VTRU - VTRD hysteresis associated with the switching between VCC and BATT if BATT < VRST and typically VHYST of hysteresis if BATT > VRST. Connect at least a 0.1F capacitor from OUT to ground (GND). Switching from VCC to BATT uses a break-before-make switch; a capacitor from OUT to GND prevents loss of power needed for clock data and RAM during switchover.
Oscillator Start Time
The MAX6909/MAX6910 oscillator typically takes 100ms to settle to its optimum operating power level after startup. To ensure the oscillator is operating, the system software should validate this by reading the seconds register. Any reading with more than 0s, from the POR value of 0s, is a validation that the oscillator is operating.
Power-On Reset (POR)
The MAX6909/MAX6910 contain an integral POR circuit that ensures all registers are reset to a known state on power-up. On initial power-up, once VOUT rises above 0.75V (typ), the POR circuit releases the registers for normal operation. Should VOUT dip to less than 1.5V (typ), the contents of the MAX6909/MAX6910 registers can no longer be guaranteed.
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller
Table 5. MAX6910 I/O and IC Sections Powered from VCC and BATT
DESCRIPTION Crystal Oscillator I/O Crystal Oscillator I/O Backup Power-Supply Input OUT (> of VCC or BATT if VCC < VRESET) Manual Reset Input Battery-On Output Watchdog Input Chip-Enable Input Power-Fail Input Ground Active Low, Open-Drain Reset Output (-OD) Active High, Push/Pull Reset Output Chip-Enable Output Power-Fail Output Alarm Output Piezo Output Crystal-Fail Output 2-Wire Bus Data I/O 2-Wire Bus Clock Main Power-Supply Input Trickle Charge FEATURES Crystal Oscillator RAM Timekeeping Registers Control Registers Crystal Fail Detect Alarm Registers Power-Fail Comparator RESET Comparator Watchdog Timer Internal Reference Power Switchover CE Circuitry Piezo Dividers/Select Register Trickle Charge Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Disabled Enabled Enabled Disabled Enabled Disabled Disabled in BATT Supply = OUT Supply = OUT Supply = OUT Supply = OUT Supply = OUT Supply = OUT Supply = OUT Supply = VCC Supply = OUT Supply = VCC Supply = VCC Supply = OUT Supply = OUT Supply = OUT PIN 9 10 1 2 6 3 7 4 5 8 18 19 17 16 14 15 11 12 13 20 1 to 20 PIN NAME X1 X2 BATT OUT MR BATT ON WDI CE IN PFI GND RESET RESET CE OUT PFO ALM PZT CX FAIL SDA SCL VCC POWER = VCC Enabled Enabled N/A N/A Enabled Enabled Enabled Enabled Enabled N/A Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled N/A Enabled VCC < VRST Enabled Enabled N/A N/A Disabled Enabled Disabled Disabled Disabled N/A Enabled Enabled Disabled Enabled Enabled Disabled Enabled Disabled Disabled N/A Disabled Power pin High impedance Pulled low Pulled to VCC Pulled to OUT Pulled low Input ignored Input ignored Input ignored Power pin Input ignored Power pin Power output pin VCC < VRST COMMENTS COMMENTS
MAX6909/MAX6910
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
Alarm Generation Registers
The alarm function generates an ALARM when the contents of the SEC, MIN, HR, DATE, MONTH, DAY, or YEAR registers match the respective alarm threshold registers. Also, the generation of the ALARM is programmable through the alarm configuration register. The alarm configuration register can be written to with an address of 94H or it can be read with an address of 95H. The alarm configuration register definition is shown in Figure 5 (register address definition). Placing a 1 in the appropriate bit enables the ALM and the alarm out status bit when the selected alarm threshold register contents match the respective timekeeping register contents. For example, writing 0000 0001 to the alarm configuration register causes the alarm pin to get triggered every minute (each time the contents of the seconds timekeeping register match the contents of the seconds alarm threshold register). Writing 0000 0010 causes the alarm to go on every hour (each time the contents of the minutes timekeeping register match the contents of the minutes alarm threshold register). Writing a 0100 1111 to the alarm configuration register, therefore, causes the alarm to be triggered on a specific second, of a specific minute, of a specific hour, of a specific date, of a specific year. The alarm output stays low until it is "cleared" by reading or writing to the alarm configuration register or by reading or writing to any of the alarm threshold registers.
VRST VCC RESET MR tRP tRP
Figure 7. Manual Reset Timing
Reset Outputs
A P's reset input starts the P in a known state. When RESET and RESET are active, all control inputs (MR, WDI, CE IN, and the 2-wire interface) are disabled. The MAX6909/MAX6910 P supervisory circuit asserts a reset to prevent code-execution errors during power-up, power-down, and brownout conditions. RESET, opendrain active low, and RESET (push-pull active high) are guaranteed to be active for 0V < VCC < VRST, provided VOUT is greater than 1V. Once VCC exceeds the reset threshold, an internal timer keeps RESET and RESET active for the reset timeout period (tRP); after this interval, RESET becomes inactive (high) and RESET becomes inactive (low). If a brownout condition occurs (VCC dips below the reset threshold), RESET and RESET become active. Each time RESET and RESET are asserted, they are held active for the reset timeout period. The MAX69_ _EO30 is optimized to monitor 3.0V 10% power supplies. Except when MR is asserted, reset does not occur until VCC falls below 2.7V (3.0V - 10%), but is guaranteed to occur before the power supply falls below +2.5V. The MAX69_ _EO33 is optimized to monitor 3.3V 10% power supplies. Except when MR is asserted, reset does not occur until VCC falls below 3.0V (3.0V is just above 3.3V - 10%), but is guaranteed to occur before the power supply falls below 2.8V. See the Maximum Transient Duration vs. Reset Comparator Overdrive graph in the Typical Operating Characteristics.
Minutes Register (Alarm Out Status)
An alarm out status bit is available if it is desired to use the alarm function as a polled alarm instead of connecting directly to the ALM output pin. Bit D7 in the minutes timekeeping register contains the status of the ALM output with a 1 indicating the alarm function has triggered and zero indicating no triggered alarm.
Manual Reset Input
Many microprocessor-based products require manualreset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. With the MAX6909/MAX6910, a logic low on MR asserts reset. Reset remains asserted while MR is low, and for tRP (Figure 7) after it returns high. MR has an internal pullup resistor of typically 50k, so it can be left open if it is not used. Internal debounce circuitry requires a minimum low time on the MR input of 1s with 100ns (typ) minimum glitch immunity.
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller
Negative-Going VCC Transients The MAX6909/MAX6910 are relatively immune to shortduration negative transients (glitches) while issuing resets to the P during power-up, power-down, and brownout conditions. Therefore, resetting the P when VCC experiences only small glitches is usually not recommended. Maximum transient duration vs. reset comparator overdrive (see the Typical Operating Characteristics) shows the maximum pulse period that can occur on VCC for which reset pulses are NOT generated. The graph was produced using negative-going VCC pulses, starting at 3.6V and ending below the reset threshold by the magnitude indicated (reset comparator overdrive). The graph shows the typical maximum pulse width a negative-going VCC transient can have without causing a reset. As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 60mV below the reset threshold and lasts for 60s or less does not cause a reset pulse to be issued. A capacitor of at least 0.1F mounted close to the VCC pin provides additional transient immunity. Interfacing to Microprocessors with Bidirectional Reset Pins Microprocessors with bidirectional reset pins, such as the Motorola 68HC11 series, can contend with the MAX6909/MAX6910 RESET or RESET outputs. If, for example, the RESET output is driven high and the P wants to pull it low, indeterminate logic levels may result. To correct this, connect a 4.7k resistor between the RESET output and the P reset I/O as shown in Figure 8. Buffer the RESET output to other system components. The positive voltage supply for the RESET pin is VCC. If VCC drops, then so does the VOH of this pin.
Battery-On Output
The battery-on output, BATT ON, is an open-drain output indicator of when the MAX6909/MAX6910 are powered from the backup battery input, BATT. When VCC falls below the reset threshold, VRST, and below VBATT, OUT switches from V CC to BATT and BATT ON is asserted. When VCC rises above VBATT or the reset threshold, VRST, OUT reconnects to VCC and BATT ON is deasserted.
MAX6909/MAX6910
Watchdog Input
In the MAX6909/MAX6910, the watchdog circuit monitors the P's activity. Data bit D4 in the configuration register controls the selection of the watchdog timeout period. The power-up default is 1.6s (D4 = 0). If D4 is set to 1, then the watchdog timeout period is changed to 200ms. Data bit D7 in the configuration register is the watchdog enable function. A logic 0 disables the watchdog function and a logic 1 enables the watchdog function. The power-on reset state of WD EN is logic 0, meaning the watchdog function is disabled. When D4 is set to 1, the first watchdog timeout period following a reset cycle is always 1.6s and reverts to 200ms after the first WDI transition. This is to allow the P to recover after a RESET interrupt. If the P does not toggle the WDI within the register-selectable watchdog timeout period, RESET and RESET are asserted for 200ms. At the same time, bits D4 and D7 in the configuration register are reset. These bits have to be rewritten to enable the watchdog and short timeout function again. While RESET and RESET are asserted, all control inputs to the MAX6909/MAX6910 are disabled (MR, CE IN, WDI, and the 2-wire interface). Figure 9 shows the watchdog timing relationship.
BUFFERED RESET TO OTHER SYSTEM VRST VCC tRP VCC VCC RESET tWD 4.7k RESET WDI tWDI tWDS
MAX6909/ MAX6910
RESET
GND
GND RESET
Figure 8. Interfacing to Microprocessors with Bidirectional Reset I/O
Figure 9. Watchdog Timing Relationship
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
START
SET WDI HIGH PROGRAM CODE
MAX6909/ MAX6910
CHIP-ENABLE OUTPUT CONTROL P
OUT
SUBROUTINE OR PROGRAM LOOP SET WDI LOW
RESET GENERATOR CE IN P CE OUT
N
RETURN
Figure 10. Watchdog Flow Diagram
Figure 11. Chip-Enable Transmission Gate
Watchdog Software Considerations There is a way to help the watchdog-timer monitor software execution more closely, which involves setting and resetting the watchdog input at different points in the program rather than "pulsing" the watchdog input high-low-high or low-high-low. This technique avoids a "stuck" loop, in which the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out. Figure 10 shows an example of how the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. If the program should "hang" in any subroutine, the problem would quickly be corrected since the I/O is continually set low and the watchdog timer is allowed to time out, causing a reset to be issued.
Chip-Enable Signal Gating
Internal gating of chip-enable (CE) signals prevents erroneous data from corrupting CMOS RAM in the event of an undervoltage condition. The MAX6909/MAX6910 use a transmission gate from CE IN to CE OUT. During normal operation (reset not asserted), the transmission gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short CE propagation delay from CE IN to CE OUT enables the MAX6909/MAX6910 to be used with most microprocessors. If CE IN is low when reset asserts, CE OUT remains low for typically tRCE to permit completion of the current write cycle. Figure 11 shows the chip-enable transmission gate.
Chip-Enable Input The CE transmission gate is disabled and CE IN is high impedance (disabled mode) while reset is asserted. During a power-down sequence when VCC goes below the reset threshold, the CE transmission gate disables, and CE IN immediately becomes high impedance if the voltage at CE IN is a logic high. If CE IN is logic low when reset asserts, the CE transmission gate disables at the moment CE IN goes high or tRCE after reset asserts (tRCE), whichever occurs first (Figure 12). This permits the current write cycle to complete during power-down. The CE transmission gate remains disabled and CE IN remains high impedance (regardless of CE IN activity) for (tRP), the reset timeout period any time a reset is generated. While disabled, CE IN is high impedance. When the CE transmission gate is enabled, the impedance of CE IN appears as a load in series with the load at CE OUT. The propagation delay through the CE transmission gate depends on VCC, the source impedance of the driver connected to CE IN, and the loading on CE OUT. The CE propagation delay is measured from the 50% point on CE IN to the 50% point on CE OUT using a 50 driver and 10pF of load capacitance (Figure 14), and is typically 5ns. For minimum propagation delay, minimize the capacitive load at CE OUT, and use a lowoutput-impedance driver. Chip-Enable Output When the CE transmission gate is enabled, the impedance of CE OUT is equivalent to a resistor in series with the source driving CE IN. In the disabled mode, the transmission gate is off and an active pullup connects CE OUT to OUT (Figure 12). This pullup turns off when the transmission gate is enabled.
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
VRST VCC VRST VRST VRST
CE OUT VBATT tRP tRCE VBATT VCC
RESET
tRP
CE IN
Figure 12. Chip-Enable Timing
MR CE OUT tRCE tRP
VCC VCC BATT 3.6V
tRP
MAX6909/ MAX6910
25 EQUIVALENT SOURCE IMPEDANCE 50 50 CABLE CE IN 50 GND CE OUT 50pF CL*
RESET
CE IN
Figure 13. Chip-Enable Timing Including MR
Power-Fail Comparator
The MAX6909/MAX6910 PFI is compared to an internal reference. If the PFI voltage is less than the power-fail threshold (VPFT), PFO goes low. The power-fail comparator is intended for use as an undervoltage detector to signal a failing power supply and can monitor either positive or negative supplies using a voltage-divider to PFI (Figure 26). However, the comparator does not need to be dedicated to this function because it is completely separate from the rest of the circuitry. Any time VCC < VRST, PFO is forced low, regardless of the state of PFI. Any time VCC > VRST and RESET is active low (during the reset timeout period), PFO is forced high, regardless of the state of PFI. If the comparator is unused, connect PFI to VCC and leave PFO floating. Figure 15 shows PFI and PFO timing.
*CL INCLUDES LOAD CAPACITANCE AND SCOPE PROBE CAPACITANCE.
Figure 14. CE Propagation-Delay Test Circuit
VCC VRST
VBATT tRST
RESET PFO
PFI VPFT
Figure 15. PFI and PFO Timing ______________________________________________________________________________________ 23
I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
Piezo Transducer Output Drive
The push-pull, piezo transducer drive output, PZT, is selectable through the configuration register for frequencies of 1.024kHz, 2.048kHz, 4.096kHz, or 8.192kHz (Table 6). Bits D0 and D1 control which frequency outputs to PZT. If in battery backup mode (when VCC falls below the reset threshold and below VBATT), the PZT output is disabled to high impedance to prevent battery drain from the backup battery on the BATT pin. Table 7 lists the piezo transducer control bits. Bit D3, the PZT SEL bit, selects whether the ALM, alarm output, controls when the selected PZT frequency is gated to PZT or whether control is given to the PZT CNTL bit, bit D2. If D3 = 1, then the ALM controls gating of the selected PZT frequency to PZT. When the alarm is triggered, the selected frequency stays on PZT until the alarm is cleared by writing to or reading from the alarm configuration register. If D3 = 0, then the PZT CNTL bit, D2, determines when and for how long the selected frequency appears at PZT. Bit D2, the PZT CNTL bit, controls whether the selected frequency is gated to PZT, provided D3 = 0. D2 = 1 gates the selected frequency to PZT and D2 = 0 inhibits the selected frequency (PZT remains low). Anytime a frequency is selected to be gated through to the PZT output, it is modulated by a 1Hz square wave. The PZT output then turns on for 0.5s and off for 0.5s. Since the human ear is particularly sensitive to changes in condition, switching a sound on and off makes it more noticeable than a continuous sound of the same frequency. The PZT output swings between VCC and GND through the output stage's on-resistance, ROUT_PZT. To allow flexibility of the PZT output to work with many different types of piezo buzzers, ROUT_PZT is designed to be as low as practical. To minimize peak currents into the piezo buzzer, an external current-limiting resistor Rs may be required. Ipeak is now equal to V CC / (Rs + ROUT_PZT). Rs can be adjusted to reduce the sound amplitude from the external piezo buzzer. The value of Rs varies for each application and should be chosen at the prototype design stage with the piezo buzzer installed in a cavity approximating its final housing. The typical value of ROUT_PZT is calculated from VOUT / IPZT, where IPZT is the average of the sink and source currents. Figure 16 is the piezo transducer functional diagram.
Table 6. Piezo Transducer Selectable Frequencies
D1 (PZT FREQ) 0 0 1 1 D0 (PZT FREQ) 0 1 0 1 PZT TYPICAL FREQUENCY (kHz) 1.024 2.048 4.096 8.19
MAX6909/ MAX6910
ROUT_PZT PZT Rs PIEZO BUZZER
VPZT
Figure 16. Piezo Transducer Functional Diagram
Table 7. Piezo Transducer Control Bits
D3 (PZT SEL) 0 0 1 1 D2 (PZT CNTL) 0 1 0 1 PZT CNTL bit, D2, has control PZT CNTL bit, D2, has control ALM has control, D2 is ignored; assume alarm triggered ALM has control, D2 is ignored; assume alarm cleared by reading the alarm configuration register CONDITION Low Selected frequency Selected frequency Low PZT
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
START CONDITION (S) tLOW BIT 7 MSB (A7) BIT 6 (A6) BIT 0 LSB (R/W) ACKNOWLEDGE (A) STOP CONDITION (P)
tSU:STA
1/fSCL
tBUF
tr
tf
tHD:STA
tSU:DAT
tHD:DAT
tVD:DAT
tSU:STO
Figure 17. 2-Wire Bus Timing Diagram
TIME_OUT_CLR 1Hz_CLK CLR CNT_UP Q1 TIME_OUT
neous communication from the microprocessor. Figure 17 is the 2-wire bus timing diagram.
Timeout Feature
The purpose of the bus timeout is to reset the serial bus interface and change the SDA line from an output to an input, which releases the SDA line from being held low. This is necessary when the MAX6909/MAX6910 are transmitting data and become stuck at logic low. If the SDA line is stuck low, any other device on the bus is not able to communicate. The logic above, shown in Figure 18, is intended to illustrate the timeout feature. If an I2C transaction takes more than 1s (minimum timout period), a timeout condition occurs. When a timeout condition is observed, the I2C interface resets to the IDLE state and waits for a new I2C transaction. In order to complete the 31-byte burst read/write from the RAM before an I 2C timeout, the minimum SCL frequency must be 0.32kHz. A valid start condition sets Time_Out_CLR = 1 and the counting begins. A valid stop condition returns Time_Out_CLR = 0 and disables the up/down counter. Figure 19 shows the normal 2-wire bus operation. Figure 20 illustrates what happens when the SDA line is stuck low for two clock cycles of 1Hz_CLK during a valid bus transaction. Depending on when the actual valid bus transaction begins relative to the 1Hz CLK, the timeout period is either t1 = 2s or t2 = 1s.
SCL SDA CNT_DOWN
1 = BUS TIMEOUT RESET SERIAL INTERFACE 0 = NO BUS TIMEOUT Q0
Figure 18. Timeout Simplified Functional Diagram
Crystal-Fail Output
The open-drain, crystal-fail output, CX FAIL, alerts the user when the 32.768kHz crystal has failed due to a loss of 30 contiguous cycles, typical, of the 32.768kHz clock. If CX FAIL enable (D7) in the alarm configuration register is set to 1, then the crystal-fail detect circuit is enabled; if D7 = 0, the crystal-fail detect circuit is disabled. When CX FAIL, D7 in the CX status register is 1, a crystal failure has been detected and CX FAIL, open-drain output, goes low. The CX FAIL output and the CX FAIL bit in the CX status register are both cleared by reading to the CX status register.
Test Configuration Register
This is a read-only register.
2-Wire Interface
The MAX6909/MAX6910 use a bidirectional 2-wire serial interface. The two lines are SDA and SCL. Both lines must be connected to a positive supply through individual pullup resistors. Data transfers can only be initiated when the bus is not busy (both SDA and SCL are high). When VCC is less than VRST, communication with the serial bus is terminated and inactive to prevent erro-
Bit Transfer
One data bit is transferred for each clock pulse. The data on SDA must remain stable during the high portion of the clock pulse as changes in data during this time are interpreted as control signals (Figure 21).
______________________________________________________________________________________
25
I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
1Hz_CLK
TIME_OUT_CLR
VALID START CONDITION SDA
VALID STOP CONDITION
SCL TIME_OUT
Figure 19. Normal 2-Wire Bus Operation
1Hz_CLK
TIME_OUT_CLR
VALID START CONDITION SDA
VALID START CONDITION
SCL
TIME_OUT
t1 t2
RESET SERIAL BUS INTERFACE
Figure 20. Timeout 2-Wire Bus Operation
SDA
SDA SDA
SCL DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED
SCL
S START CONDITION
P STOP CONDITION
SCL
Figure 21. Bit Transfer 26
Figure 22. START and STOP Conditions
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller
START and STOP Conditions
Both SDA and SCL remain high when the bus is not busy. A high-to-low transition of SDA, while SCL is high, is defined as the START (S) condition. A low-to-high transition of the data line while SCL is high is defined as the STOP (P) condition (Figure 22).
Address/Command Byte
The command byte is shown in Figure 24. The MSB (bit 7) must be a logic 1. If it is zero, writes to the MAX6909/ MAX6910 are disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits 1 through 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or a read operation (output) if logic 1. The command byte is always input starting with the MSB (bit 7).
MAX6909/MAX6910
Acknowledge
The number of data bytes between the START and STOP conditions for the transmitter and receiver are unlimited. Each 8-bit byte is followed by an acknowledge bit. The acknowledge bit is a high-level signal put on SDA by the transmitter, during which time the master generates an extra acknowledge-related clock pulse. A slave receiver that is addressed must generate an acknowledge after each byte it receives. Also, a master receiver must generate an acknowledge after each byte it receives that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable low during the high period of the acknowledge clock pulse (setup and hold times must also be met). A master receiver must signal an end of the data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave SDA high to enable the master to generate a STOP condition.
Reading from the Timekeeping Registers
The timekeeping registers (seconds, minutes, hours, date, month, day, and year) can be read either with a single read or a burst read. The century register can only be read with a single read. Since the real-time clock runs continuously and a read takes a finite amount of time, there is the possibility that the clock counters could change during a read operation, thereby reporting inaccurate timekeeping data. In the MAX6909/MAX6910, each clock register's data is buffered by a latch. Clock register data is latched by the 2-wire bus read command (on the falling edge of SCL when the slave acknowledge bit is sent after the address/command byte has been sent by the master to read a timekeeping register). Collision-detection circuitry ensures that this does not happen coincident with a seconds counter update to ensure accurate time data is being read. This avoids time data changes during a read operation. The clock counters continue to count and keep accurate time during the read operation. If single reads are to be used to read each of the timekeeping registers individually, then it is necessary to do some error checking on the receiving end. The potential for error is the case when the seconds counter increments before all the other registers are read out. For example, suppose a carry of 13:59:59 to 14:00:00 occurs during single read operations of the timekeeping registers. Then, the net data could become 14:59:59, which is erroneous real-time data. To prevent this with single-read operations, read the seconds register first (initial seconds) and store this value for future comparison. When the remaining timekeeping registers have been read out, read the seconds register again (final seconds). If the initial seconds value is 59, check that the final seconds value is still 59; if not, repeat the entire single-read process for the timekeeping registers. A comparison of the initial seconds value with the final seconds value can indicate if there was a bus delay problem in reading the timekeeping data (difference should always be 1s or less). Using a 100kHz bus speed, sequential single reads would take under 2.5ms to read all seven of the timekeeping registers, plus a second read of the seconds register.
27
Slave Address Byte
Before any data is transmitted on the bus, the device that should respond is addressed first. The first byte sent after the start (S) procedure is the address byte. The MAX6909/MAX6910 act as a slave transmitter/receiver. Therefore, SCL is only an input clock signal and SDA is a bidirectional data line. The slave address for the MAX6909/MAX6910 is shown in Figure 23.
1 BIT 7
1
0
1
0
0
0
RD/W BIT 0
Figure 23. MAX6909/MAX6910 2-Wire Slave Address Byte
7 1
6 RAM /CLK
5 A5
4 A4
3 A3
2 A2
1 A1
0 RD /W
Figure 24. Address/Command Byte
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
The most accurate way to read the timekeeping registers is to do a burst read. In the burst read, the main timekeeping registers (seconds, minutes, hours, date, month, day, year) and the control register are read sequentially, in the order listed with the seconds register first. They must be all read out as a group of eight registers, with 8 bits each, for proper execution of the burst read function. All seven timekeeping registers are latched upon the receipt of the burst read command. Worst-case errors that can occur between the actual time and the read time is 1s, assuming the entire burst read is done in less than 1s. If single write operations are to be used to write to each of the timekeeping registers, then error checking is needed. If the seconds register is to be updated, update it first and then read it back and store its value as the initial seconds. Update the remaining timekeeping registers and then read the seconds register again (final seconds). If initial seconds were 59, ensure they are still 59. If initial seconds were not 59, ensure that final seconds are within 1s of initial seconds. If the seconds register is not to be written to, then read the seconds register first and save it as initial seconds. Write to the required timekeeping registers and then read the seconds register again (final seconds). If initial seconds were 59, ensure they are still 59. If initial seconds were not 59, ensure that final seconds are within 1s of initial seconds. Although both single writes and burst writes are possible, the most accurate way to write to the timekeeping registers is to do a burst write. In the burst write, the main timekeeping registers (seconds, minutes, hours, date, month, day, year) and the control register are written to sequentially. They must be all written to as a group of eight registers, with 8 bytes each, for proper execution of the burst write function. All seven timekeeping registers are simultaneously loaded into the input buffer at the end of the 2-wire bus write operation. The worst-case error that can occur between the actual time and the write time update is 1s. Figure 25 shows MAX6909/MAX6910 data transfer.
Writing to the Timekeeping Registers
The time and date can be set by writing to the timekeeping registers (seconds, minutes, hours, date, month, day, year, and century). To avoid changing the current time by an incomplete write operation, the current time value is buffered from being written directly to the timekeeping registers. The timekeeping registers continue to count, and on the next rising edge of the 1Hz seconds clock, the new data is loaded into the timekeeping registers. The new value will be incremented on the next rising of the 1Hz seconds clock. Collision-detection circuitry ensures that this does not happen coincident with a seconds register update to ensure accurate time data is being written. This avoids time data changes during a write operation. An incomplete write operation aborts the time update procedure and the contents of the input buffer are discarded.
ADDRESS/COMMAND BYTE S BIT 7...............................BIT 0 ACK BIT 7-BIT SLAVE ADDRESS 0 AS SINGLE WRITE ADDRESS/COMMAND BYTE S BIT 7...............................BIT 0 ACK BIT 7-BIT SLAVE ADDRESS 0 AS SINGLE READ ADDRESS/COMMAND BYTE S BIT 7...............................BIT 0 ACK BIT 7-BIT SLAVE ADDRESS 0 AS BURST WRITE ADDRESS/COMMAND BYTE S BIT 7...............................BIT 0 ACK BIT 7-BIT SLAVE ADDRESS 0 AS BURST READ BIT 7......................................BIT 0 ACK BIT 1R 11111 1 AS BIT 7......................................BIT 0 ACK BIT 1R 11111 0 AS BIT 7......................................BIT 0 ACK BIT 1R ADDR 1 AS BIT 7......................................BIT 0 ACK BIT 1R ADDR 0 AS
BIT 7...................BIT 0 ACK BIT 8_BIT DATA AS
P
S
BIT 7.........................BIT 0 ACK BIT 7-BIT SLAVE ID 1 AS
BIT 7.........................BIT 0 AM 8_BIT DATA
P
BIT 7.................BIT 0 ACK BIT FIRST 8_BIT DATA AS
BIT 7...................BIT 0 ACK BIT LAST 8_BIT DATA AS P
S
BIT 7.........................BIT 0 ACK BIT 7-BIT SLAVE ID 1 AS
BIT 7....................BIT 0 ACK BIT FIRST 8_BIT DATA A
M
SLAVE ADDRESS: 1101000 ADDR: 5-BIT RAM OR REGISTER ADDRESS R: RAM/REGISTER SELECTION BIT. R = 0 WHEN REGISTER IS SELECTED; R = 1 WHEN RAM IS SELECTED. S: START CONDITION FROM MASTER P: READ CONDITION FROM MASTER AS : ACKNOWLEDGE FROM SLAVE AM : ACKNOWLEDGE FROM MASTER AM : NOT ACKNOWLEDGE FROM MASTER
BIT 7....................BIT 0 ACK BIT LAST 8_BIT DATA A
M
P
Figure 25. MAX6909/MAX6910 Data Transfer 28 ______________________________________________________________________________________
I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
R1 PFI R2 VIN VCC R1 PFI VCC
MAX6909/ MAX6910
PFO GND
R2 VIN
MAX6909/ MAX6910
PFO GND MR
PFO IS ACTIVE HIGH WHEN MONITORING A NEGATIVE SUPPLY
VTRIP = R2 x (VPFT + VPFH) x
1 1 CC ( R1 + R2 ) - VR1
VTRIP = VPFT x R1 + R2 R2
(
) )
VL = R2 x VPFT x
1 1 CC ( R1 + R2 ) - VR1
VH = (VPFT + VPFH) x R1 + R2 R2
(
NOTE: VTRIP AND VL ARE NEGATIVE.
VCC PFO VIN VL VTRIP 0V PFO
VCC
VTRIP
VIN
VIN
a) MONITORING A NEGATIVE SUPPLY
b) MONITORING SECONDARY SUPPLY
Figure 26. Using the Power-Fail Comparator to Monitor Additional Power Supplies
Applications Information
Monitoring Additional Power Supplies
PFO can be connected to MR so that a low voltage on PFI activates RESET and RESET (Figure 26). In this configuration, when the monitored voltage causes PFI to fall below VPFT, PFO pulls MR low, causing a reset to be asserted. A 200ms reset is generated, during which PFO is forced high and MR is released. At the end of the 200ms reset, the power-fail comparator reflects the state of PFI, which if below VPFT, causes another reset.
Adding Hysteresis to the Power-Fail Comparator
The power-fail comparator has a typical input hysteresis of 30mV. This is sufficient for most applications where a power-supply line is being monitored through an external voltage-divider supply (Figure 27). If additional noise margin is desired, connect a resistor between PFO and PFI (Figure 27(a)). Select the ratio of R1 and R2 such that PFI sees VPFT when VIN falls to its trip point (VTRIP). R3 adds the additional hysteresis and should typically be more than 10 times the value of R1 or R2. The hysteresis window extends both above (VH) and below (VL) the original trip point (VTRIP).
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29
I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
VIN R1 PFI R2 C1 R3 VCC R1 PFI VIN VCC
MAX6909/ MAX6910
PFO GND
R2
C1
R3
MAX6909/ MAX6910
PFO GND
TO P VTRIP = VPFT x R1 + R2 R2 VH = (VPFT + VPFH) (R1)
TO P
(
)
VTRIP = VPFT x R1 + R2 R2
(
)
1 1 1 ( R1 + R2 + R3 ) VD R3
1 1 1 ( R1 + R2 + R3 ) 1 1 1 CC ( R1 + R2 + R3 ) - VR3
VH = R1 x (VPFT + VPFH) x
VL = R1 x VPFT x
VD = DIODE FORWARD-VOLTAGE DROP VL = VTRIP
VCC PFO VIN VL VTRIP VH PFO
VCC
0V
VTRIP
VH
VIN
a) SYMMETRICAL HYSTERESIS
b) R3 HYSTERESIS ONLY ON RISING VIN
Figure 27. Adding Hysteresis to the Power-Fail Comparator
Connecting an ordinary signal diode in series with R3 (Figure 27(b)) causes the lower trip point (VL) to coincide with the trip point without hysteresis (V TRIP), so that the entire hysteresis window occurs above VTRIP. This method provides additional noise margin without compromising the accuracy of the power-fail threshold when the monitored voltage is falling. It is useful for accurately detecting when a voltage falls past a threshold. The current through R1 and R2 should be at least 1A to ensure that the 100nA (max over temperature) PFI input current does not shift the trip point. R3 should be larger than 82k so it does not load down the PFO pin. Capacitor C1 is optional and adds noise rejection.
Early Power-Fail Warning Using the PFI Input
Critical systems often require an early warning indicating that power is failing. This warning provides time for the P to store vital data and take care of any additional "housekeeping" functions before the power supply gets too far out of tolerance for the P to operate reliably. If access to the unregulated supply is feasible, the power-fail comparator input (PFI) can be connected to the unregulated supply through a voltage-divider, with the power-fail comparator output (PFO) providing the nonmaskable interrupt (NMI) to the P (Figure 28).
30
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller
Pin Configuration
UNREGULATED SUPPLY R1 PFI R2 PFO REGULATOR
MAX6909/MAX6910
TOP VIEW
VCC BATT 1 20 VCC 19 RESET 18 RESET 17 CE OUT
MAX6909/ MAX6910
OUT 2 BATT ON 3
GND
CE IN 4 PFI 5 MR 6
MAX6909/ MAX6910
16 PFO 15 PZT 14 ALM 13 SCL 12 SDA 11 CX FAIL
TO P
WDI 7 GND 8 X1 9 X2 10
Figure 28. Using the Power-Fail Comparator to Generate a Power-Fail Warning
Selector Guide
PART MAX6909EO30 MAX6909EO33 MAX6910EO30 MAX6910EO33 RESET THRESHOLD (TYP) 2.63 2.93 2.63 2.93 TRICKLE CHARGER No No Yes Yes
QSOP
Chip Information
TRANSISTOR COUNT: 35,267 PROCESS: BiCMOS
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31
I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller MAX6909/MAX6910
Typical Operating Circuit
12V VBATT 6.98k 1k USER RESET PFI PFO PZT BATT ON WDI 3.3V 3.3V RPU CONTROLLER RPU = tr/CBUS RPU VBATT 3.0V 0.1F MR BATT SCL SDA OUT CE RESET INTO NMI CMOS RAM 3.3V 3.3V MULTIFUNCTION ASIC 47k CE CE OUT 1F* CX FAIL CE IN RESET RESET X2 ALM BATTERY-ON INDICATOR 150k
MAX6909/ MAX6910
3.3V VCC X1 CRYSTAL 3.3V 47k 3.3V 47k 0.01F
PFO CX FAIL
RST * USE A LOW-LEAKAGE CAPACITOR.
32
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I2C-Compatible Real-Time Clocks with P Supervisor and NV RAM Controller
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
MAX6909/MAX6910
21-0055
E
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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